Generally, semiconductor memory devices, such as dynamic random access memory (DRAM) devices, can store data or information therein. The data or information is stored in and read out from the semiconductor memory devices. A typical single memory cell of conventional semiconductor memory devices includes one capacitor and one transistor. The capacitor of the semiconductor memory device generally includes a storage electrode, a dielectric layer and a plate electrode. The larger the capacitance of the capacitor, the larger the storage capacitance of the capacitor.
As memory devices become more highly integrated, the size of the memory devices has also decreased. To provide sufficient storage capacitance of the semiconductor memory device, the capacitors typically include a plane shape in an early stage and have been gradually developed to have various shapes such as boxes, cylinders, fins, and the like. In order to increase the storage capacitance, capacitors having a double or multiple cylindrical shape have been developed and heights of the capacitors have been augmented. Capacitors illustrating various of these aspects are discussed in, for example, U.S. Pat. No. 5,923,973 and U.S. Patent Publication No. 2002-56867.
FIGS. 1A to 1E are cross-sections illustrating processing steps in the fabrication of capacitors having double cylindrical shapes as discussed in U.S. Pat. No. 5,923,973. Referring now to FIG. 1A, a substrate 5 is divided into an active region and a field region by an isolation layer 10 on the substrate 5. After a gate oxide layer 25 and a gate electrode 30 are formed on the active region, source and drain regions 15 and 20 are formed at surface portions of the substrate 5 between the gate electrodes 30.
A word line 35 is formed on the field region and a base layer 40 is formed on the substrate 5 using an oxide. A first insulating layer 45 and a second insulating layer 50 are successively formed on the base layer 40. The first insulating layer 45 may include an oxide and the second insulating layer 50 may include a nitride.
Referring now to FIG. 1B, a third insulating layer 55 is formed on the second insulating layer 50 using an oxide and the third insulating layer 55 is partially etched to form a capacitor hole exposing at least a portion of the second insulating layer 50 through the third insulating layer 55. The drain region 15 is disposed under the capacitor hole. A first conductive layer 60 including polysilicon is formed on a floor and an inner sidewall of the capacitor hole and on the third insulating layer 55.
Referring now to FIG. 1C, a fourth insulating layer 65 is formed on the first conductive layer 60 in the capacitor hole. The fourth insulating layer 65, the first conductive layer 60, the second insulating layer 50, the first insulating layer 45 and the base layer 40 are successively etched to form a contact hole exposing at least a portion of the drain region 15.
A second conductive layer 75 is formed on the fourth insulating layer 65 and the first conductive layer 60 in the contact hole. Here, a plug 70 contacting the drain region 15 is formed in the contact hole. The fourth insulating layer 65 includes an oxide and the second conductive layer 75 includes polysilicon.
Referring now to FIG. 1D, the second conductive layer 75 and the first conductive layer 60 are etched until at least a portion of the third insulating layer 55 is exposed to thereby form a storage electrode including a double cylindrical shape. The storage electrode includes the fourth insulating layer 65.
Referring now to FIG. 1E, the fourth insulating layer 65 and the third insulating layer 55 are removed to complete the storage electrode including the first conductive layer 60 and the plug 70. A dielectric layer 80 and a plate electrode 85 are successively formed on the storage electrode and the second insulating layer 50 to complete the capacitor having a double cylindrical shape.
In the above-described method, the processes for forming the capacitor may be complicated as the plug and the conductive patterns are simultaneously formed by at least two fabrication steps. Furthermore, since the plug for coupling the capacitor to the contact region is relatively high, a contact failure may occur between the capacitor and the contact region when the plug does not make precise contact with the contact region. When the contact failure of the capacitor occurs, the storage electrode of the capacitor may not be electrically coupled to the contact region and may thereby cause a failure of the semiconductor device.
Since the storage electrode of a conventional capacitor includes the plug through the cylindrical conductive layer, a surface area extension of the storage electrode may be limited. Thus, the capacitance of the capacitor including the storage electrode may also be limited. Accordingly, improved capacitors and methods of fabricating them may be desired.